Method of semiconductor integrated circuit fabrication
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality o...
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Main Authors | , , , |
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Format | Patent |
Language | English |
Published |
17.04.2018
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Subjects | |
Online Access | Get full text |
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Summary: | A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features. |
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Bibliography: | Application Number: US201715430852 |