Shared command address (C/A) bus for multiple memory channels
A shared command/address (C/A) bus for memory devices in a multi-channel configuration can enable reducing the number of pins and signal lines in a memory subsystem. In one embodiment, a memory controller includes hardware logic to generate commands to access a plurality of memory devices via a plur...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
10.04.2018
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Subjects | |
Online Access | Get full text |
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Summary: | A shared command/address (C/A) bus for memory devices in a multi-channel configuration can enable reducing the number of pins and signal lines in a memory subsystem. In one embodiment, a memory controller includes hardware logic to generate commands to access a plurality of memory devices via a plurality of channels and input/output (I/O) circuitry to transmit command/address (C/A) information for the commands to the plurality of memory devices over a single C/A bus for the plurality of channels. In one embodiment, double-speed strobe signal lines can also enable reducing the number of pins and signal lines in a memory subsystem. |
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Bibliography: | Application Number: US201615278802 |