SRAM cell with dynamic split ground and split wordline

An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access tran...

Full description

Saved in:
Bibliographic Details
Main Author Wong Robert C
Format Patent
LanguageEnglish
Published 03.04.2018
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.
Bibliography:Application Number: US201615287274