Self aligned conductive lines

A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel material on the second hardmask, and patterning a mask on the layer of sacrificial material. A first sacrificial mandrel and a second sacrificia...

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Bibliographic Details
Main Authors Penny Christopher J, Felix Nelson M, DeSilva Anuja E, Saulnier Nicole A, Clevenger Lawrence A, Kanakasabapathy Sivananda K, Quon Roger A, Mignot Yann A. M, Burns Sean D
Format Patent
LanguageEnglish
Published 06.03.2018
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel material on the second hardmask, and patterning a mask on the layer of sacrificial material. A first sacrificial mandrel and a second sacrificial mandrel and a gap are formed. A layer of spacer material is deposited in the gap. Portions of the first sacrificial mandrel and the second sacrificial mandrel are removed, and exposed portions of the second hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. The second hardmask, the spacers, and the planarizing layer are removed. Exposed portions of the insulator layer are removed to form a trench in the insulator layer, and the trench is filled with a conductive material.
Bibliography:Application Number: US201715677447