Chip-stacked semiconductor package and method of manufacturing the same

• Main Authors: Cho Tae-Je, Kang Un-Byoung, Roh Byung-Hyug
• Format: Patent
• Language: English
• Published: 27.02.2018
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other.