Semiconductor device and semiconductor device manufacturing method

A first parallel pn layer in which first n-type regions and first p-type regions are disposed in a plan view layout of stripes in an element active portion. A second parallel pn layer has a plan view layout of stripes oriented in the same direction as that of the stripes of the first parallel pn lay...

Full description

Saved in:
Bibliographic Details
Main Authors Niimura Yasushi, Sakata Toshiaki, Takenoiri Shunji
Format Patent
LanguageEnglish
Published 06.02.2018
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:A first parallel pn layer in which first n-type regions and first p-type regions are disposed in a plan view layout of stripes in an element active portion. A second parallel pn layer has a plan view layout of stripes oriented in the same direction as that of the stripes of the first parallel pn layer in a breakdown voltage structure portion. Corner portions of the first parallel pn layer has a plan view shape where stepped regions formed by shortening the length of the first n-type and p-type regions in steps are disposed in a stepwise arrangement. The stepped regions continue with a second parallel pn layer via an intermediate region lower in average impurity concentration than the first parallel pn layer.
Bibliography:Application Number: US201615068534