Apparatuses and methods to translate a logical thread identification to a physical thread identification

Methods and apparatuses relating to translating a logical thread identification to a physical thread identification. A processor may include a plurality of cores that include a buffer, and a thread mapping hardware unit to: return a physical thread identification in response to a logical thread iden...

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Bibliographic Details
Main Authors Duran Gonzalez Alejandro, Guim Bernat Francesc
Format Patent
LanguageEnglish
Published 06.02.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Methods and apparatuses relating to translating a logical thread identification to a physical thread identification. A processor may include a plurality of cores that include a buffer, and a thread mapping hardware unit to: return a physical thread identification in response to a logical thread identification sent to a buffer of a first core when the buffer includes a logical to physical thread mapping for the logical thread identification, and send a request to the buffers of the other cores when the first core's buffer does not include the logical to physical thread mapping for the logical thread identification, wherein each of the other cores are to send an unknown identification response if their buffer does not include the logical thread identification and at least one of the other cores is to send the physical thread identification to the first core if its buffer includes the logical thread identification.
Bibliography:Application Number: US201615055234