Maintaining packet order in a parallel processing network device

An instruction execution processor has an input to receive instructions associated with maintaining a queue for storing packet identifiers (IDs) corresponding to packets being processed by a network device. A memory coupled to the instruction execution processor is for storing instructions received...

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Bibliographic Details
Main Authors Babitsky Eliya, Eldar Alon
Format Patent
LanguageEnglish
Published 06.02.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:An instruction execution processor has an input to receive instructions associated with maintaining a queue for storing packet identifiers (IDs) corresponding to packets being processed by a network device. A memory coupled to the instruction execution processor is for storing instructions received at the input of the instruction execution processor and not executed by the instruction execution processor. An instruction feedback processor is coupled to the instruction execution processor. The instruction feedback processor is configured to, in response to receiving an output from the instruction execution processor, identify one or more instructions, stored in the memory, that correspond to a new packet ID at the head of the queue, and feed back, to the input of the instruction execution processor, the one or more identified instructions.
Bibliography:Application Number: US201514838336