Method and apparatus for a zero voltage processor sleep state

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power...

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Bibliographic Details
Main Authors Fischer Stephen A, Naveh Alon, George Varghese, Jahagirdar Sanjeev, Milstrey Robert, Conrad John B, Rotem Shai
Format Patent
LanguageEnglish
Published 23.01.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
Bibliography:Application Number: US201514966708