Power efficient processor architecture

In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the...

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Bibliographic Details
Main Authors Makineni Srihari, Herdrich Andrew J, Illikkal Rameshkumar G, Iyer Ravishankar, Moses Jaideep, Srinivasan Sadagopan
Format Patent
LanguageEnglish
Published 09.01.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
WIRELESS COMMUNICATIONS NETWORKS
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Summary:In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
Bibliography:Application Number: US201615134770