Bottom self-aligned via

A method for an interconnect structure including: forming a hard mask layer on a semiconductor substrate having a wiring line; patterning the hard mask layer to form a patterned hard mask layer having a hard mask layer opening; depositing a dielectric stack on the patterned hard mask layer and in th...

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Bibliographic Details
Main Authors Topaloglu Rasit O, Angyal Matthew S, Lustig Naftali E
Format Patent
LanguageEnglish
Published 02.01.2018
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method for an interconnect structure including: forming a hard mask layer on a semiconductor substrate having a wiring line; patterning the hard mask layer to form a patterned hard mask layer having a hard mask layer opening; depositing a dielectric stack on the patterned hard mask layer and in the hard mask layer opening; patterning the dielectric stack to form a via opening aligned with the hard mask layer opening and to expose the wiring line through the via opening and the hard mask layer opening, a bottom of the via opening defined by the hard mask layer having the hard mask layer opening; and filling the via opening and the hard mask layer opening with a metal to form a via in contact with the wiring line.
Bibliography:Application Number: US201615268604