System on a chip including a management unit for allocating and deallocating an address range

A processor system (10) includes: a first memory controller (16) that controls writing/reading data to/from a first memory (60); a second memory controller (17) that controls writing/reading data to/from a second memory (70); a first processor (13) that inputs and outputs the data from and to the fi...

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Bibliographic Details
Main Authors Ito Yoshiyuki, Tsuda Tetsuji
Format Patent
LanguageEnglish
Published 19.12.2017
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor system (10) includes: a first memory controller (16) that controls writing/reading data to/from a first memory (60); a second memory controller (17) that controls writing/reading data to/from a second memory (70); a first processor (13) that inputs and outputs the data from and to the first memory through a bus (14); a second processor (11) that inputs and outputs processed data from and to the second memory through the bus; and a management unit 32 that deallocates an address range corresponding to the second memory from the first process and allocates the address range to the second processor.
Bibliography:Application Number: US201715427207