Mechanism to avoid hot-L1/cold-L2 events in an inclusive L2 cache using L1 presence bits for victim selection bias

A processor includes a processing core, an L1 cache, operatively coupled to the processing core, the L1 cache comprising an L1 cache entry to store a data item, an L2 cache, inclusive with respect to the L1 cache, the L2 cache comprising an L2 cache entry corresponding to the L1 cache entry, an acti...

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Bibliographic Details
Main Authors Aurangabadwala Zainulabedin, Sodani Avinash, Vinod Krishna N
Format Patent
LanguageEnglish
Published 05.12.2017
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor includes a processing core, an L1 cache, operatively coupled to the processing core, the L1 cache comprising an L1 cache entry to store a data item, an L2 cache, inclusive with respect to the L1 cache, the L2 cache comprising an L2 cache entry corresponding to the L1 cache entry, an activity flag associated with the L2 cache entry, the activity flag indicating an activity status of the L1 cache entry, and a cache controller to, in response to detecting an access operation with respect to the L1 cache entry, set the flag to an active status.
Bibliography:Application Number: US201514671411