Precharge circuitry for semiconductor memory device

A semiconductor memory apparatus may include a memory cell circuit, a data latch circuit, and a first stage amplification circuit. The data latch circuit may be electrically coupled to the memory cell circuit by a bit line. The data latch circuit may latch data transferred through the bit line. The...

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Bibliographic Details
Main Authors Choi Eun Ji, Park Kang Woo
Format Patent
LanguageEnglish
Published 28.11.2017
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A semiconductor memory apparatus may include a memory cell circuit, a data latch circuit, and a first stage amplification circuit. The data latch circuit may be electrically coupled to the memory cell circuit by a bit line. The data latch circuit may latch data transferred through the bit line. The data latch circuit may output latched data to an input/output line in response to a cell select signal. The data first stage amplification circuit may generate driving data to a voltage level of an external power supply voltage in response to a voltage level of the input/output line. The data first stage amplification circuit may precharge the input/output line to a voltage level lower than the external power supply voltage and higher than a ground voltage in response to a precharge signal.
Bibliography:Application Number: US201615345101