DRAM access in self-refresh state

Systems and method are directed to accessing a Dynamic Random Access Memory (DRAM) system. A DRAM controller is designed to determine that a DRAM bank of a DRAM system is in a self-refresh state and allow one or more commands to access the DRAM bank without exiting the self-refresh state. The DRAM c...

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Bibliographic Details
Main Authors Kunapareddy SankaraRao, Saifuddin Mosaddiq
Format Patent
LanguageEnglish
Published 21.11.2017
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Systems and method are directed to accessing a Dynamic Random Access Memory (DRAM) system. A DRAM controller is designed to determine that a DRAM bank of a DRAM system is in a self-refresh state and allow one or more commands to access the DRAM bank without exiting the self-refresh state. The DRAM controller may select these one or more commands, based on one or more of a clock frequency, traffic conditions related to requests for accessing the DRAM bank, or a command type. The one or more commands may include at least one of read (RD), write (WR), or precharge (PRE) commands received while the DRAM bank is in the self-refresh state.
Bibliography:Application Number: US201615249132