Managed instruction cache prefetching

Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common...

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Bibliographic Details
Main Authors Lopez Pedro, Latorre Fernando, Xekalakis Polychronis, Madriles Gimeno Carlos, Hyuseinova Mirem, Martinez Raul, Gomez Requena Crispin, Marcuello Pedro, Stavrou Kyriakos A, Codina Josep M, Gonzalez Antonio, Kotselidis Christos E, Gibert Codina Enric, Martinez Vicente Alejandro, Lupon Marc, Pavlou Demos, Ortega Daniel, Tournavitis Georgios, Magklis Grigorios
Format Patent
LanguageEnglish
Published 07.11.2017
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.
Bibliography:Application Number: US201113995649