Managing semiconductor memory array leakage current

• Main Authors: Davis John D, Chan Yuen H, Penth Silke, Bunce Paul A, Schmitt David E, Werner Tobias, Yavoich Brian J
• Format: Patent
• Language: English
• Published: 17.10.2017
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

A memory array can include a global evaluation circuit, a local evaluation circuit for evaluating a voltage level of a local bit line and a wake transistor configured to connect an output of the local evaluation circuit to a global bit line (GBL) of the global evaluation circuit. The global evaluation circuit can include a holding circuit. The wake transistor can be turned on in response to a read signal, and remain on while the GBL is precharged to a logical "high" voltage. Memory cells connected to the at least one local bit line can be addressed, and the local bit line can be pulled to a logical "low" voltage for a first time period. The GBL can be pulled to a logical low voltage for a second time period, and the holding circuit polarity can be reversed during a third time period.