Equalizing erase depth in different blocks of memory cells

A memory device and associated techniques provide a uniform erase depth for different blocks of memory cells which are at different distances from pass gates of a voltage source. In one approach, a voltage of a source side select gate transistor of a memory string is a decreasing function of the dis...

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Bibliographic Details
Main Authors Dong Yingda, Zhang Zhengyi, Zeng Caifu, Pang Liang, Yu Xuehong
Format Patent
LanguageEnglish
Published 10.10.2017
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory device and associated techniques provide a uniform erase depth for different blocks of memory cells which are at different distances from pass gates of a voltage source. In one approach, a voltage of a source side select gate transistor of a memory string is a decreasing function of the distance. In another approach, a magnitude or duration of an erase voltage at a source end of a memory string is an increasing function of the distance. Adjacent blocks can be arranged in subsets and treated as being at a common distance. In another approach, an additional erase pulse can be applied when the distance of the block exceeds a threshold. Other variables such as initial erase voltage and step size can also be adjusted as a function of distance.
Bibliography:Application Number: US201615367549