Method, apparatus and system for configuring a protocol stack of an integrated circuit chip

Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Per...

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Main Authors Wood Aimee D, Ananthakrishnan Avinash N, Song Marcus W, Boswell Brent R, Spry Bryan L, Rangaraj Deepak M, Letendre Adam E, Hayes Robert J
Format Patent
LanguageEnglish
Published 15.08.2017
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Abstract Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.
AbstractList Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.
Author Spry Bryan L
Ananthakrishnan Avinash N
Wood Aimee D
Rangaraj Deepak M
Hayes Robert J
Boswell Brent R
Letendre Adam E
Song Marcus W
Author_xml – fullname: Wood Aimee D
– fullname: Ananthakrishnan Avinash N
– fullname: Song Marcus W
– fullname: Boswell Brent R
– fullname: Spry Bryan L
– fullname: Rangaraj Deepak M
– fullname: Letendre Adam E
– fullname: Hayes Robert J
BookMark eNqNyz0OwjAMQOEMMPB3Bx8AhlIEYgWBWJiAiaGyXKeNKHaUuAO3pwMHYHrL96ZuJCo8cc8rW6v1EjBGTGh9BpQa8icbv8FrAlLxoelTkAYQYlJT0g6yIb1A_cAhiHEzzFwDhUR9MKA2xLkbe-wyL36dOTif7sfLiqNWnCMSC1v1uO135aYotod1-Qf5AiXhPNM
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
Physics
ExternalDocumentID US9734116B2
GroupedDBID EVB
ID FETCH-epo_espacenet_US9734116B23
IEDL.DBID EVB
IngestDate Fri Jul 19 15:15:14 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US9734116B23
Notes Application Number: US201514658021
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170815&DB=EPODOC&CC=US&NR=9734116B2
ParticipantIDs epo_espacenet_US9734116B2
PublicationCentury 2000
PublicationDate 20170815
PublicationDateYYYYMMDD 2017-08-15
PublicationDate_xml – month: 08
  year: 2017
  text: 20170815
  day: 15
PublicationDecade 2010
PublicationYear 2017
RelatedCompanies Intel Corporation
Spry Bryan L
Ananthakrishnan Avinash N
Wood Aimee D
Rangaraj Deepak M
Hayes Robert J
Boswell Brent R
Letendre Adam E
Song Marcus W
RelatedCompanies_xml – name: Spry Bryan L
– name: Wood Aimee D
– name: Boswell Brent R
– name: Letendre Adam E
– name: Hayes Robert J
– name: Song Marcus W
– name: Ananthakrishnan Avinash N
– name: Rangaraj Deepak M
– name: Intel Corporation
Score 3.1086388
Snippet Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip...
SourceID epo
SourceType Open Access Repository
SubjectTerms CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Title Method, apparatus and system for configuring a protocol stack of an integrated circuit chip
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170815&DB=EPODOC&locale=&CC=US&NR=9734116B2
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8NAEB5Kfd40KtYXc5CcDCbm1R6K0KSlCH1gWyl4KNlNokFIQpPg33d2baMXvW42S3bCPL7dmW8Abt1YZ5zpoaZH3NQsp21rAXMNrUPeOqR3CCLIBNmxM1xYT0t72YBkWwsjeUI_JTkiaRQnfS-lvc5_DrF8mVtZ3LOEhrLHwbzrqxt0bLjk4WzV73X704k_8VTP6y5m6viZwBKZa8PpkbXeEVG0oNnvv_REUUr-26MMjmB3Soul5TE0olSBA2_beE2B_dHmvluBPZmgyQsa3ChhcQKvI9n1-Q6DXBJ3VwUGaYjfnMxIQSgSxo2TN1mAiAEKKoaM_jdSIMg_MItpOtY0ESHyZM2rpET-nuSngIP-3Btq9L2rWjarxazemXkGzTRLo3NAKzIYF1X_rB1ZDzoPuG66nbYTM5PwCTNa0PpzmYt_nl3CoRCyOFM17CtolusquianXLIbKc4vpFaTNg
link.rule.ids 230,309,786,891,25594,76903
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8NAEB5KfdSbVsX6nIPkZDAxr_ZQhCQtUfvCtlLwULKbRIOQhCbFv-9kbasXve6L3VlmZr_dmW8Brq1IYZwpgayEXJN1s2nIPrNUuUXeOqA-BBFEgOzA9Kb648yYVSBe58IIntBPQY5IGsVJ3wthr7OfSyxXxFbmtyymovS-O2m70godqxZ5OENy7XZnNHSHjuQ47elYGjwTWCJzrZo2WestixChQEovdpmUkv32KN192B7RYElxAJUwqUPNWX-8Vofd_uq9uw47IkCT51S4UsL8EF774tfnG_QzQdy9zNFPAvzmZEY6hCJh3Ch-EwmI6GNJxZDSfiMdBPkHphE1xw1NRIA8XvBlXCB_j7MjwG5n4ngyzXe-kc18Ot6sTDuGapIm4QmgHqqMl1n_rBnqdwr3uaJZraYZMY3wCVMb0PhzmNN_6q6g5k36vXnvYfB0BnulwMv7VdU4h2qxWIYX5KALdilE-wWrw5Yg
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Method%2C+apparatus+and+system+for+configuring+a+protocol+stack+of+an+integrated+circuit+chip&rft.inventor=Wood+Aimee+D&rft.inventor=Ananthakrishnan+Avinash+N&rft.inventor=Song+Marcus+W&rft.inventor=Boswell+Brent+R&rft.inventor=Spry+Bryan+L&rft.inventor=Rangaraj+Deepak+M&rft.inventor=Letendre+Adam+E&rft.inventor=Hayes+Robert+J&rft.date=2017-08-15&rft.externalDBID=B2&rft.externalDocID=US9734116B2