Method and apparatus for mapping a logical address between memories of a storage drive based on write frequency rankings

A storage drive including a first and second memories and a controller. The second memory has a write cycle lifetime that is less than a write cycle lifetime of the first memory. Each of the first and second memories includes solid-state memory. The controller: determines a write frequency for a fir...

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Bibliographic Details
Main Author Sutardja Pantas
Format Patent
LanguageEnglish
Published 08.08.2017
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A storage drive including a first and second memories and a controller. The second memory has a write cycle lifetime that is less than a write cycle lifetime of the first memory. Each of the first and second memories includes solid-state memory. The controller: determines a write frequency for a first logical address; and based on the write frequency, determines a write frequency ranking for the first logical address. The write frequency ranking is based on a weighted time-decay average of write counts or an average of elapsed times of write cycles. The controller also: determines whether the write frequency ranking is greater than a lowest write frequency ranking of logical addresses of the first memory; and if the write frequency ranking of the first logical address is greater, maps the logical address with the lowest write frequency ranking in the first memory to the second memory.
Bibliography:Application Number: US201514872260