Memory circuit

It is provided a memory circuit comprising n inputs; n+1 columns, wherein each column is connected to a plurality of memory cells; wherein the i-th (1≦i≦n−1) column is configured to be conductive connectable to the i-th input or to the (i+1)-th input or neither to the i-th input nor to the (i+1)-th...

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Bibliographic Details
Main Authors Chan Yuen H, Penth Silke, Schmitt David E, Werner Tobias
Format Patent
LanguageEnglish
Published 18.07.2017
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:It is provided a memory circuit comprising n inputs; n+1 columns, wherein each column is connected to a plurality of memory cells; wherein the i-th (1≦i≦n−1) column is configured to be conductive connectable to the i-th input or to the (i+1)-th input or neither to the i-th input nor to the (i+1)-th input; a first FET and a second FET in series configured for connecting the i-th column to a defined voltage level; wherein a first gate signal renders the first FET conductive, if the i-th column is not in conductive connection with the i-th input; wherein a second gate signal renders the second FET conductive, if the i-th column is not in conductive connection with the (i+1)-th input.
Bibliography:Application Number: US201615182178