Process monitoring for gate cut mask

A method of monitoring critical dimensions of gate electrode structures is provided including providing a substrate, forming a gate electrode pattern on the substrate comprising forming gate electrode lines parallel to each other, forming a mask layer on the gate electrode pattern and forming openin...

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Bibliographic Details
Main Authors Smith Elliot John, Chan Nigel
Format Patent
LanguageEnglish
Published 20.06.2017
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method of monitoring critical dimensions of gate electrode structures is provided including providing a substrate, forming a gate electrode pattern on the substrate comprising forming gate electrode lines parallel to each other, forming a mask layer on the gate electrode pattern and forming openings in the mask layer in a crosswise direction with respect to the direction of the parallel gate electrode lines, thereby exposing portions of the gate electrode pattern, etching exposed portions of the gate electrode pattern through the mask layer openings, thereby obtaining a negative image of the mask layer openings, removing remaining portions of the mask layer, and monitoring dimensions of the mask layer openings.
Bibliography:Application Number: US201615055954