Method of using dummy patterns for overlay target design and overlay control

Methodologies for using dummy patterns for overlay target design and overlay control are provided. Embodiments include providing a first dummy pattern on a first layer as an outer overlay target for an integrated circuit (IC); providing a pattern associated with a second dummy pattern on a second la...

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Bibliographic Details
Main Authors Zhou Yue, Park Dongsuk, Karakoy Mert
Format Patent
LanguageEnglish
Published 25.04.2017
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ANGLES
MEASURING AREAS
MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
MEASURING LENGTH, THICKNESS OR SIMILAR LINEARDIMENSIONS
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
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Summary:Methodologies for using dummy patterns for overlay target design and overlay control are provided. Embodiments include providing a first dummy pattern on a first layer as an outer overlay target for an integrated circuit (IC); providing a pattern associated with a second dummy pattern on a second layer as a target for measuring overlay; and utilizing a scanning electron microscope (SEM) to obtain an overlay measurement between the first and second dummy patterns.
Bibliography:Application Number: US201615057727