Self-aligned dielectric isolation for FinFET devices

Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height...

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Bibliographic Details
Main Authors Bergendahl Marc Adam, Standaert Theodorus Eduardus, Yang Chih-Chao, Cheng Kangguo, Cai Xiuyu, Xie Ruilong, Koburger, III Charles William, Horak David Vaclav, Khakifirooz Ali, Ponoth Shom
Format Patent
LanguageEnglish
Published 18.04.2017
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.
Bibliography:Application Number: US201414538401