Self-aligned dielectric isolation for FinFET devices
Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height...
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Main Authors | , , , , , , , , , |
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Format | Patent |
Language | English |
Published |
18.04.2017
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Subjects | |
Online Access | Get full text |
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Summary: | Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed. |
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Bibliography: | Application Number: US201414538401 |