High performance interconnect
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over...
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Main Authors | , , , , , , , , , , , , , , , , , , , , , , , |
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Format | Patent |
Language | English |
Published |
18.04.2017
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Subjects | |
Online Access | Get full text |
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Abstract | A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state |
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AbstractList | A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state |
Author | Das Abhishek Gupta Ashish Shah Rahul R Johnson Simon P Geetha Vedaraman Nale William Harry Swanson Jeffrey C Spink Aaron T Fahim Bahaa Safranek Robert J Jue Darren S Ramanujan Raj K Das Sharma Debendra Kumar Arvind A Iyer Sitaraman V Maddox Robert A Spagna Fulvio Liu Yen-Cheng Hum Herbert H Iyer Venkatraman Dhillon Yuvraj S Blankenship Robert G Willey Jeff Beers Robert |
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Notes | Application Number: US201314060191 |
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Snippet | A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be... |
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SubjectTerms | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
Title | High performance interconnect |
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