High performance interconnect

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over...

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Bibliographic Details
Main Authors Jue Darren S, Iyer Sitaraman V, Hum Herbert H, Willey Jeff, Gupta Ashish, Iyer Venkatraman, Swanson Jeffrey C, Blankenship Robert G, Das Sharma Debendra, Geetha Vedaraman, Safranek Robert J, Shah Rahul R, Das Abhishek, Maddox Robert A, Fahim Bahaa, Kumar Arvind A, Spink Aaron T, Nale William Harry, Johnson Simon P, Beers Robert, Liu Yen-Cheng, Spagna Fulvio, Ramanujan Raj K, Dhillon Yuvraj S
Format Patent
LanguageEnglish
Published 18.04.2017
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state
Bibliography:Application Number: US201314060191