Semiconductor memory device with selectively located air gaps

A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the prel...

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Bibliographic Details
Main Authors Park Hae-Jung, Hwang Chang-Youn, Park Dae-Sik, Joe Ill-Hee, Kwon Se-Han, Kang Sang-Kil
Format Patent
LanguageEnglish
Published 11.04.2017
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Summary:A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.
Bibliography:Application Number: US201615092076