Partial, self-biased isolation in semiconductor devices

• Main Authors: Zuo Jiang-Kai, Yang Hongning, Lin Xin
• Format: Patent
• Language: English
• Published: 04.04.2017
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a body region disposed in the semiconductor substrate and to which a voltage is applied during operation and in which a channel is formed during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the body region. The depletion region reaches a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. The depletion region establishes an electrical link between the buried doped isolation layer and the body region such that the buried doped isolation layer is biased at a voltage level lower than the voltage applied to the body region.