High voltage transistor with reduced isolation breakdown

Devices and methods for forming a device are disclosed. The device includes a substrate with a device region having a length and a width direction. An isolation region surrounds the device region of which an isolation edge abuts the device region. A transistor is disposed in the device region. The t...

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Bibliographic Details
Main Authors Leung Ying Keung, Tan Shyue Seng
Format Patent
LanguageEnglish
Published 04.04.2017
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Devices and methods for forming a device are disclosed. The device includes a substrate with a device region having a length and a width direction. An isolation region surrounds the device region of which an isolation edge abuts the device region. A transistor is disposed in the device region. The transistor includes a gate disposed between first and second source/drain (S/D) regions. A silicide block is disposed on the transistor. The silicide block covers at least the isolation edge adjacent to the gate. The silicide block prevents formation of a silicide contact at least at the isolation edge adjacent to the gate.
Bibliography:Application Number: US201514840075