Clock tree circuit and memory controller

A clock tree circuit Including a first clock source, generating a first signal, and a first tree circuit. The first clock tree circuit includes a first driving stage for receiving the first signal, a second driving stage, connected to the first driving stage, a third driving stage, connected to the...

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Bibliographic Details
Main Authors Chiang Chen-Feng, Yao Chih-Tsung, Liou Ming-Shi, Chen Kai-Hsin
Format Patent
LanguageEnglish
Published 31.01.2017
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A clock tree circuit Including a first clock source, generating a first signal, and a first tree circuit. The first clock tree circuit includes a first driving stage for receiving the first signal, a second driving stage, connected to the first driving stage, a third driving stage, connected to the second driving stage, and a metal connection element, coupled between different nodes of the third driving stage and configured as a short-circuited element.
Bibliography:Application Number: US201514980362