Semiconductor memory apparatus performing a refresh operation

A semiconductor memory apparatus may include a refresh mode control circuit configured to enable a row address increase signal when all banks capable of being designated by a bank address in a refresh operation are all designated. The semiconductor memory apparatus may also include and a row address...

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Bibliographic Details
Main Author Ko Jae Bum
Format Patent
LanguageEnglish
Published 17.01.2017
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A semiconductor memory apparatus may include a refresh mode control circuit configured to enable a row address increase signal when all banks capable of being designated by a bank address in a refresh operation are all designated. The semiconductor memory apparatus may also include and a row address generation circuit configured to increase a value of a row address when the row address increase signal is enabled.
Bibliography:Application Number: US201414515821