Method and apparatus for fabricating wafer by calculating process correction parameters
A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated...
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Main Author | |
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Format | Patent |
Language | English |
Published |
10.01.2017
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Subjects | |
Online Access | Get full text |
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Summary: | A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer. |
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Bibliography: | Application Number: US201313749740 |