Method and apparatus for fabricating wafer by calculating process correction parameters

A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated...

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Bibliographic Details
Main Author Habets Boris
Format Patent
LanguageEnglish
Published 10.01.2017
Subjects
APPARATUS SPECIALLY ADAPTED THEREFOR
BASIC ELECTRIC ELEMENTS
CALCULATING
CINEMATOGRAPHY
COMPUTING
CONTROL OR REGULATING SYSTEMS IN GENERAL
CONTROLLING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
ELECTROGRAPHY
FUNCTIONAL ELEMENTS OF SUCH SYSTEMS
HOLOGRAPHY
MATERIALS THEREFOR
MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS
ORIGINALS THEREFOR
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHYSICS
REGULATING
SEMICONDUCTOR DEVICES
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Summary:A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.
Bibliography:Application Number: US201313749740