Symmetrical extension junction formation with low-k spacer and dual epitaxial process in finFET device

• Main Authors: Yamashita Tenko, Basker Veeraraghavan S, Liu Zuoguang, Yeh Chun-Chen
• Format: Patent
• Language: English
• Published: 20.12.2016
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A technique relates to a dual epitaxial process a device. A first spacer is disposed on a substrate, dummy gate, and hardmask. A first area extends in a first direction from the gate and a second area extends in an opposite direction. A doped intermediate spacer is disposed on the first spacer. A first region is opened on the substrate by removing first spacer and intermediate spacer at the first region. A first epitaxial layer is disposed in the first region. The intermediate spacer is removed from first area. A second spacer is disposed on the intermediate spacer. A second region is opened on the substrate by removing the first spacer, intermediate spacer, and second spacer. A second epitaxial layer is disposed in second region. The width of the second epitaxial layer is enlarged by annealing causing dopant in the intermediate spacer layer to flow into the second epitaxial layer.