Nonvolatile memory device comprising page buffer and program verification operation method thereof

A nonvolatile memory device is provided which includes a page buffer unit. The page buffer unit includes a first page buffer including a first A latch configured to store first upper bit data and a first B latch configured to store first lower bit data, and a second page buffer including a second A...

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Bibliographic Details
Main Authors Lee Dae Yeal, Kang Dongku
Format Patent
LanguageEnglish
Published 13.12.2016
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A nonvolatile memory device is provided which includes a page buffer unit. The page buffer unit includes a first page buffer including a first A latch configured to store first upper bit data and a first B latch configured to store first lower bit data, and a second page buffer including a second A latch configured to store second upper bit data and a second B latch configured to store second lower bit data. A set pulse may be applied to both the first A latch and the second B latch, or to both the second A latch and the first B latch. The non-volatile memory device may provide high write performance and may respond within a time out period of a handheld terminal.
Bibliography:Application Number: US201514853488