Nanowire semiconductor device including lateral-etch barrier region

A semiconductor device includes a semiconductor-on-insulator wafer having a buried oxide layer. The buried oxide layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel p...

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Bibliographic Details
Main Authors Yamashita Tenko, Basker Veeraraghavan S, Liu Zuoguang, Yeh Chun-Chen
Format Patent
LanguageEnglish
Published 22.11.2016
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A semiconductor device includes a semiconductor-on-insulator wafer having a buried oxide layer. The buried oxide layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried oxide layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.
Bibliography:Application Number: US201514950011