Integrated bit-line airgap formation and gate stack post clean

Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called "2-d flat cell" flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work...

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Bibliographic Details
Main Authors Purayath Vinod R, Ingle Nitin K, Thakur Randhir, Venkataraman Shankar
Format Patent
LanguageEnglish
Published 15.11.2016
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called "2-d flat cell" flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.
Bibliography:Application Number: US201414448059