Silicided bit line for reversible-resistivity memory

A three-dimensional (3D) non-volatile memory array having a silicide bit line and method of fabricating is disclosed. The fabrication technique may comprise forming a metal silicide for at least a portion of the bit line. The device has reversible resistivity material between the word lines and the...

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Bibliographic Details
Main Authors Fujiwara Kan, Iizuka Toshihiro, Kikuchi Shin, Tanaka Yoichiro, Futase Takuya, Nishida Akio, Petti Christopher J
Format Patent
LanguageEnglish
Published 13.09.2016
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A three-dimensional (3D) non-volatile memory array having a silicide bit line and method of fabricating is disclosed. The fabrication technique may comprise forming a metal silicide for at least a portion of the bit line. The device has reversible resistivity material between the word lines and the bit lines. The reversible resistivity material may be a metal oxide. The metal that is used to form the silicide may serve as an oxygen scavenger to draw oxygen away from the silicon, thus preventing formation of silicon oxide between the reversible resistivity material and the bit line. The metal silicide may also help prevent formation of a depletion layer in silicon in the bit line.
Bibliography:Application Number: US201514795211