Reduced memory iterative baseband processing

A receiver, including: a posteriori probability demodulator configured to receive an input digital signal and output demodulated data; a deinterleaver configured to deinterleave the demodulated data; a forward error correction (FEC) decoder configured to error correct the demodulated data; a FEC enc...

Full description

Saved in:
Bibliographic Details
Main Author Engin Nur
Format Patent
LanguageEnglish
Published 23.08.2016
Subjects
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
Online AccessGet full text

Cover

More Information
Summary:A receiver, including: a posteriori probability demodulator configured to receive an input digital signal and output demodulated data; a deinterleaver configured to deinterleave the demodulated data; a forward error correction (FEC) decoder configured to error correct the demodulated data; a FEC encoder configured to encode the error corrected demodulated data; an interleaver configured to interleave the FEC encoded data and output the interleaved FEC encoded data to the posteriori probability demodulator; and a symbol compressor/decompressor configured to compress symbol data from the a posteriori demodulator and store the compressed data in a symbol memory and configured to decompress compressed symbol data stored in the symbol memory.
Bibliography:Application Number: US201414461030