Method and structure for transistors using gate stack dopants with minimal nitrogen penetration

Embodiments of the present invention provide CMOS structures and methods of gate formation that combine a keep-cap scheme in which a protective layer is maintained on a PFET during a replacement metal gate process that utilizes an NFET-first process flow. Selective nitridation is used to provide nit...

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Bibliographic Details
Main Authors Kannan Balaji, Kwon Unoh, Rajaram Rekha
Format Patent
LanguageEnglish
Published 16.08.2016
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Embodiments of the present invention provide CMOS structures and methods of gate formation that combine a keep-cap scheme in which a protective layer is maintained on a PFET during a replacement metal gate process that utilizes an NFET-first process flow. Selective nitridation is used to provide nitrogen to the NFET while the PFET is protected from nitrogen by the keep-cap. Additional dopants are provided to the NFET using a gate stack dopant material (GSDM) layer.
Bibliography:Application Number: US201414513725