Dynamic subroutine linkage optimizing shader performance
Allocation of memory registers for shaders by a processor is described herein. For each shader, registers are allocated based on the shader's level of complexity. Simpler shader instances are restricted to a smaller number of memory registers. More complex shader instances are allotted more reg...
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Main Authors | , , , , |
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Format | Patent |
Language | English |
Published |
12.07.2016
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Subjects | |
Online Access | Get full text |
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