Compiler directed cache coherence for many caches generated from high-level language source code

• Main Authors: MASON JEFFREY M, PUTNAM ANDREW R, SUNDARARAJAN PRASANNA
• Format: Patent
• Language: English
• Published: 28.06.2016
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Approaches for generating and operating an electronic system. High-level language (HLL) source code is compiled into equivalent intermediate language program code. The compilation determines a plurality of caches for storing data referenced by the HLL source. Flush instructions are inserted in the intermediate language program. Each flush instruction references one of caches and is inserted in the intermediate language program immediately following an instruction that is last to write to that cache. The intermediate language program is translated into a hardware description that specifies the plurality of caches, circuits for processing data in the caches, and for each of the caches a flush interface that initiates writing data from the cache to a main memory in response to a flush signal. The timing of the respective flush signal is determined based on placement of one of the one or more flush instructions in the intermediate language program.