Bit error rate reduction buffer, method and apparatus

A disclosed example bit error rate reduction buffer comprises a data recovery circuit including differential bit pair inputs and differential bit pair outputs, a CRC circuit including differential bit pair inputs, differential bit pair outputs and a fault-isolation indicator, and a serializer includ...

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Bibliographic Details
Main Author THAYER LARRY J
Format Patent
LanguageEnglish
Published 29.03.2016
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:A disclosed example bit error rate reduction buffer comprises a data recovery circuit including differential bit pair inputs and differential bit pair outputs, a CRC circuit including differential bit pair inputs, differential bit pair outputs and a fault-isolation indicator, and a serializer including differential bit pair inputs and differential bit pair outputs. The differential bit pair outputs of the data recovery circuit being coupled to the differential bit pair inputs of the CRC circuit, the differential bit pair outputs of the CRC circuit being coupled to the differential bit pair inputs of the serializer, the differential bit pair inputs of the data recovery circuit to be driven by a first HSS link, the different bit pair outputs of the serializer to drive a second HSS link; and the fault-isolation indicator of the CRC circuit to indicate a fault when a fault is detected by the CRC circuit.
Bibliography:Application Number: US20100831082