Low latency memory access control for non-volatile memories

A memory is provided that comprises a bank of non-volatile memory cells configured into a plurality of banklets. Each banklet in the plurality of banklets can be enabled separately and independently of the other banklets in the bank of non-volatile memory cells. The memory further comprises peripher...

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Bibliographic Details
Main Authors RAJAMANI KARTHICK, MUKUNDAN JANANI, FERREIRA ALEXANDRE P, KUANG JENTE B
Format Patent
LanguageEnglish
Published 15.03.2016
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory is provided that comprises a bank of non-volatile memory cells configured into a plurality of banklets. Each banklet in the plurality of banklets can be enabled separately and independently of the other banklets in the bank of non-volatile memory cells. The memory further comprises peripheral banklet circuitry, coupled to the bank of a non-volatile memory array, that is configured to enable selected subsets of bit lines within a selected banklet within the plurality of banklets. Moreover, the memory comprises banklet select circuitry, coupled to the peripheral banklet circuitry, that is configured to select data associated with a selected banklet for reading out from the banklet or writing to the banklet.
Bibliography:Application Number: US201314082624