Semiconductor memory device including non-volatile memory, cache memory, and computer system

In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configu...

Full description

Saved in:
Bibliographic Details
Main Authors KIM SUN-GYEUM, AHN JUN-WHAN, CHOI KI-YOUNG, KWON HYEOK-MAN, KWON YOUNG-JUN
Format Patent
LanguageEnglish
Published 02.02.2016
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.
Bibliography:Application Number: US201313790113