DRAM controller for variable refresh operation timing

A method for selection of a DRAM refresh timing in a DRAM memory system is disclosed. The method may include running a workload for a first number of refresh intervals using a first DRAM refresh timing and making a first workload throughput measurement for the first number of refresh intervals. The...

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Bibliographic Details
Main Authors KIM KYU-HYOUN, MUKUNDAN JANANI, HUNTER HILLERY C
Format Patent
LanguageEnglish
Published 02.02.2016
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A method for selection of a DRAM refresh timing in a DRAM memory system is disclosed. The method may include running a workload for a first number of refresh intervals using a first DRAM refresh timing and making a first workload throughput measurement for the first number of refresh intervals. The method may also include running the workload for a second number of refresh intervals using a second DRAM refresh timing and making a second workload throughput measurement for the second number of refresh intervals. The method may further include deciding if the first throughput measurement is greater than the second throughput measurement, and then selecting the first DRAM refresh timing as a selected DRAM refresh timing, or deciding if the second throughput measurement is greater than the first throughput measurement, then selecting the second DRAM refresh timing as the selected DRAM refresh timing.
Bibliography:Application Number: US201514823094