Reset generation circuit for scan mode exit

A reset generation circuit of an integrated circuit uses a scan data input pin as a scan mode exit control, which is enabled only when the IC reset pin of the device is active. The reset generation circuit allows a TAP controller to be scan testable yet at the same time the circuit provides a method...

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Bibliographic Details
Main Author JINDAL ANURAG
Format Patent
LanguageEnglish
Published 15.12.2015
Subjects
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:A reset generation circuit of an integrated circuit uses a scan data input pin as a scan mode exit control, which is enabled only when the IC reset pin of the device is active. The reset generation circuit allows a TAP controller to be scan testable yet at the same time the circuit provides a method to exit scan mode without requiring a power-up sequence or an extra pin.
Bibliography:Application Number: US201414225446