Stack packages and methods of manufacturing the same

A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereo...

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Bibliographic Details
Main Authors BAE JIN HO, BAE HAN JUN
Format Patent
LanguageEnglish
Published 24.11.2015
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors.
Bibliography:Application Number: US201314082441