Multi-port memory that supports multiple simultaneous write operations

It is determined whether more than one half of a plurality of data blocks are addressed to a same primary memory bank in a plurality of memory banks. If not more than one half of the data blocks in the plurality of data blocks are addressed to the same primary memory bank, the plurality of data bloc...

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Bibliographic Details
Main Author ROITSHTEIN AMIR
Format Patent
LanguageEnglish
Published 24.11.2015
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:It is determined whether more than one half of a plurality of data blocks are addressed to a same primary memory bank in a plurality of memory banks. If not more than one half of the data blocks in the plurality of data blocks are addressed to the same primary memory bank, the plurality of data blocks are written to appropriate ones of the primary memory banks in a single clock cycle. If more than one half of the data blocks are addressed to the same primary memory bank, (i) a subset of the data blocks addressed to the same primary memory bank are written to the same primary memory bank, and (ii) one or more remaining data blocks of the data blocks addressed to the same primary memory bank are written to an additional memory bank.
Bibliography:Application Number: US201313939973