Alignment of integrated circuit chip stack

The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligni...

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Bibliographic Details
Main Authors YU ROY R, KHANNA VIJAYESHWAR D, SRI-JAYANTHA SRI M, COLGAN EVAN G, CORDES STEVEN A, WISNIEFF ROBERT L, LIN QINGHUANG, EDELSTEIN DANIEL C, LATZKO KENNETH, SORCE PETER J
Format Patent
LanguageEnglish
Published 27.10.2015
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.
Bibliography:Application Number: US201313947543